1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an operating unit of an LCD panel and a method for operating the same, to prevent a greenish phenomenon, similar to a green color, generated on the entire screen.
2. Discussion of the Related Art
In general, an LCD device displays various images in a method of controlling light transmittance of liquid crystal cells according to a video signal. The LCD device has been generally applied to display devices for a monitor of a computer, a cellular phone, and office equipment, wherein the LCD device realizes an active matrix type of providing switching devices in respective liquid crystal cells. In this case, the switching device used for the LCD device of the active matrix type is generally formed of a thin film transistor (hereinafter, referred to as “TFT”).
FIG. 1 is a block diagram illustrating an LCD device according to the related art. As shown in FIG. 1, the LCD device according to the related art includes an LCD panel 6, a digital video card 1, a data driver 3, a gate driver 5, and a timing controller 2. At this time, the LCD panel has a plurality of data lines DL and a plurality of gate lines GL, wherein each data line DL is formed in perpendicular to each gate line GL. Also, a thin film transistor TFT is formed at each crossing portion of the gate and data lines GL and DL in the LCD panel 6. Then, the digital video card 1 is provided to convert analog video data into digital video data. The data driver 3 supplies the video data to the data line DL of the LCD panel 6, and the gate driver 5 sequentially operates the gate lines GL of the LCD panel 6. Furthermore, the timing controller 2 is provided to control the data driver 3 and the gate driver 5.
Herein, the LCD panel 6 includes lower and upper glass substrates and a liquid crystal layer, wherein the liquid crystal layer is formed in a method of injecting liquid crystal between the lower and upper glass substrates. Also, the plurality of gate lines GL and the plurality of data lines DL are formed on the lower glass substrate. In this state, each of the gate lines GL is in perpendicular to each of the data lines DL. Then, the thin film transistor TFT is formed at each crossing portion of the gate line GL and the data line DL, wherein the thin film transistor TFT is formed to selectively supply an image inputted from the corresponding data line DL to a liquid crystal cell Clc. For this, each thin film transistor TFT has a gate terminal being in contact with the corresponding gate line GL, a source terminal being in contact with the corresponding data line DL, and a drain terminal being in contact with a pixel electrode of the corresponding liquid crystal cell Clc.
Then, the digital video card 1 converts an analog video signal to a digital video signal suitable for the LCD panel 6, and detects a synchronous signal included in the video signal. Also, the timing controller 2 supplies the digital video data of red (R), green (G), and blue (B) provided from the digital video card 1 to the data driver 3. Furthermore, the timing controller 2 generates data and gate control signals such as a dot clock Dclk and a gate start pulse Gsp by using horizontally/vertically synchronized signals H/V inputted from the digital video card 1, thereby controlling the timing of the data driver 3 and the gate driver 5. In this state, the data control signal such as the dot clock Dclk is supplied to the data driver 3, and the gate control signal such as the gate start pulse Gsp is supplied to the gate driver 5.
In more detail, the gate driver 5 is composed of a shift register and a level shifter. At this time, the shift register sequentially generates scan pulses in response to the gate start pulse Gsp inputted from the timing controller 2, and the level shifter shifts a voltage of the scan pulse to make a level suitable for operation of the liquid crystal cell Clc. In response to the scan pulse inputted from the gate driver 5, the video data of the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the thin film transistor TFT.
In addition to the digital video data of red (R), green (G), and blue (B) from the timing controller 2, the dot clock Dclk is also inputted to the data driver 3. That is, the data driver 3 latches the digital video data of red (R), green (G), and blue (B) in synchronization with the dot clock Dclk, and then compensates the latched data according to a gamma voltage. After that, the data driver 3 converts the data compensated by the gamma voltage to analog data, and supplies the analog data to the data line DL by lines.
Hereinafter, an operating unit of an LCD panel and a method for operating the same according to the related art will be described with reference to the accompanying drawings. FIG. 2 is a block diagram illustrating a gate driver and a data driver in an LCD panel according to the related art. FIG. 3 is a block diagram illustrating the data driver of FIG. 2. FIG. 4 is a detailed block diagram illustrating one of a plurality of data drivers ICs for the data driver of FIG. 3.
As shown in FIG. 2, the LCD device according to the related art includes an LCD panel 10, a data driver 20, a gate driver 30, and a timing controller 40. At this time, the LCD panel 10 is formed in a matrix type having a plurality of liquid crystal cells Clc. Also, the LCD panel 10 includes a plurality of gate lines GL and a plurality of data lines DL, wherein each of the gate lines GL is formed in perpendicular to each of the data lines DL. In addition, a plurality of thin film transistors TFT are formed at respective crossing portions of the gate and data lines GL and DL. Then, the data driver 20 supplies data video signals to the data lines DL of the LCD panel 10, and the gate driver 30 sequentially operates the gate lines GL of the LCD panel 10. Also, the timing controller 40 is provided to apply a data control signal and a polarity control signal to the data driver 20, and to apply a gate control signal to the gate driver 30.
As shown in FIG. 3, the data driver 20 includes a plurality of data driver ICs 20a to 20f, which are operated with the data control signal and the polarity control signal inputted from the timing controller 40.
Specifically, as shown in FIG. 4, the data driver IC 20a is composed of a shift register array 21, a latch array 22, a digital-analog conversion (hereinafter, referred to as ‘DAC’) array 23, and an output buffer array 24. At this time, the shift register array 21 supplies sequential sampling signals. In response to the sampling signals of the shift register array 21, the latch array 22 sequentially latches pixel data VD, and simultaneously outputs the latched pixel data VD. Also, the DAC array 23 converts the pixel data VD outputted from the latch array 22 to pixel voltage signals. Then, the output buffer array 24 compensates and outputs the pixel voltage signals outputted from the DAC array 23. The data driver ICs drive the data lines of ‘k’ channel.
In this case, shift registers of the shift register array 21 sequentially shift source start pulses SSP from the timing controller 40 according to a source sampling clock signal SSC, and then outputs the shifted source start pulses SSP as the sampling signals.
Subsequently, the latch array 22 responds to the sampling signals outputted from the shift register array 21, so that the pixel data VD is sequentially sampled and latched by predetermined sizes. For this, the latch array 22 is composed of ‘k’ latches for latching the pixel data VD numbered in ‘k’, and each latch has a size corresponding to a bit number of the pixel data VD (3 bit or 6 bit). After that, the latch array 22 responds to a source output enable signal SOE outputted from the timing controller 40, thereby simultaneously outputting the latched pixel data VD numbered in ‘k’.
The DAC array 23 converts the pixel data VD outputted from the latch array 22 into the positive (+) polarity pixel voltage signal and the negative (−) polarity pixel voltage signal, and simultaneously outputs the positive (+) polarity pixel voltage signal and the negative (−) polarity pixel voltage signal. For this, the DAC array 23 includes a P (positive) decoder array 25, an N (negative) decoder array 26, and an MUX (multiplexer) array 27. At this time, the P decoder array 25 and the N decoder array 26 are connected with the latch array 22, and the MUX array 27 is provided to select an output signal from the P decoder array 25 and the N decoder array 26.
At this time, the P decoder array 25 includes P decoders of ‘k’ channel, wherein the P decoders convert the pixel data outputted from the latch array 22 into the positive (+) polarity pixel voltage signal by using positive polarity gamma voltages outputted from a gamma voltage unit (not shown), and then output the positive (+) polarity pixel voltage signal. Also, the N decoder array 26 includes N decoders of ‘k’ channel, wherein the N decoders convert the pixel data outputted from the latch array 22 into the negative (−) polarity pixel voltage signal by using negative (−) polarity gamma voltages outputted from the gamma voltage unit, and then output the negative (−) polarity pixel voltage signal. Then, multiplexers of ‘k’ channel provided to the MUX array 27 respond to the polarity control signal POL outputted from the timing controller 40, so that it is possible to selectively output the positive (+) polarity pixel voltage signal from the P decoder array 25 or the negative (−) polarity pixel voltage signal from the N decoder array 26.
For example, the polarity of the polarity control signal POL is oppositely changed by each horizontal period H. In response to the polarity of the polarity control signal POL, the MUX array 27 selectively outputs the pixel voltage signals such that the polarities of the pixel voltage signals are differently supplied in the adjacent multiplexers by each horizontal period H, for operation of a dot inversion method. Also, the output buffer array 24 includes output buffers of ‘k’ channel, in which the output buffers are provided with voltage followers respectively connected with the data lines of ‘k’ channel in series. The output buffers buffer the pixel voltage signals outputted from the DAC array 23, and provide the buffered pixel voltage signals to the data lines.
The LCD panel of the LCD device according to the related art is operated in the dot inversion method explained below with reference to FIG. 5A and FIG. 5B.
As shown in FIG. 5A and FIG. 5B, when operating the related art LCD panel in the dot inversion method, a polarity of a data signal is differently supplied to adjacent liquid crystal cells by a column line and a row line on the LCD panel. At the same time, the data signal is supplied such that the polarity of the data signal is oppositely provided to all the liquid crystal cells of the LCD panel by each frame.
That is, in case of displaying a video signal of one frame on the LCD panel in the dot inversion method, as the liquid crystal cells sequentially progress from the left in the upper side to the right in the lower side, the data signals of the positive (+) polarity and the negative (−) polarity are alternately provided to the liquid crystal cells of the LCD panel, as shown in FIG. 5A.
Then, as shown in FIG. 5B, when displaying a video signal of the next frame, the polarities of the data signals provided to the liquid crystal cells are opposite to the polarities of the data signals supplied on the prior frame.
In the dot inversion method, the polarity of the data signal is differently applied to the liquid crystal cells adjacent in the horizontal and vertical directions of the LCD panel, thereby obtaining a greater picture image than that of a frame inversion method or a line inversion method. For this reason, the dot inversion method for operating the LCD panel is generally used.
However, the operating unit of the LCD panel and the method for operating the same according to the related art have the following disadvantages.
That is, there is superior polarity in a common gate line due to the positive (+) polarity or the negative (−) polarity when charging the data by each frame, so that it may generate distortion in the data charging characteristics. As a result, the picture quality deteriorates due to the greenish phenomenon, similar to a green color, on the entire screen of the LCD panel.